• The 74HC138 decodes three binary weighted address inputs (A0, A1 and A2) into eight mutually exclusive outputs (Y 0 to Y 7). The device has three validation inputs (E 1, E 2 and E3).
• Each output will be HIGH unless E 1 and E 2 are LOW and E3 is HIGH.
• This multiple activation feature allows easy parallel expansion to a 1 of 32 decoder (5 to 32 lines) with only four ‘138 ICs and an inverter.
• The ‘138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as data input and the remaining enable inputs as strobes.
• The inputs include clamping diodes.
• This allows the use of current limiting resistors to interface inputs at voltages greater than VDC.

Specifications:

• Model Number: 74HC138D
• Case type: SOP16
• Function: Decoder
• Type: Logic integrated circuits
• Operating voltage: 2 to 6 V
• Typical supply current: 0.08mA
• Operating temperature: -40 ° C – 125 ° C
• Compatibility: CMOS input, CMOS output
• Technical sheet : https://docs.rs-online.com/8cb5/A700000007664546.pdf