ENE926-D2
ENE926-D2:
- The KB926D is an embedded controller with LPC interface to connect with host. The
embedded controller contains industrial standard 8051 microprocessor and provides function of i8042 keyboard controller basically. - LPC Low Pin Count Interface
-SIRQ supporting IRQ1, IRQ12, SCI or SMI# interrupt and one programmable IRQ provided.
-I/O Address Decoding: Legacy KBC I/O port 60h/64h , Programmable EC I/O port,62h/66h(recommend) , I/O port 68h/6Ch (sideband) , 2 Programmable 4-byte Index-I/O ports to access internal EC registers, 1 Programmable extended (debug) port I/O.
-Memory Decoding: Firmware Hub decode, LPC memory decode
-Compatible with LPC specification v1.1 - X-bus Bus Interface (XBI) : Flash Interface
-SPI flash is supported, size up to 4MB.
-SPI frequency supports 33/45/66MHz.
-New SPI command (dual read) to enhance the performance.
-The 64KB code memory can be mapped into system memory by one 16KB and one 48KB programmable pages independently.
Product Description
DESCRIPTON:
- The KB926D is an embedded controller with LPC interface to connect with host. The
embedded controller contains industrial standard 8051 microprocessor and provides function of
i8042 keyboard controller basically. The KB926D is designed with Shared-ROM architecture with - SPI flash. The EC firmware and system BIOS will exist in one SPI flash. The embedded controller
also features rich interfaces for applications, such as PS/2 interface, Keyboard Matrix, PWM, A/D
converter, D/A converter, Fan controller, SMBus controller, GPIO controllers and extension interface for future applications.
Features :
- LPC Low Pin Count Interface
-SIRQ supporting IRQ1, IRQ12, SCI or SMI# interrupt and one programmable IRQ provided.
-I/O Address Decoding: Legacy KBC I/O port 60h/64h , Programmable EC I/O port,62h/66h(recommend) , I/O port 68h/6Ch (sideband) , 2 Programmable 4-byte Index-I/O ports to access internal EC registers, 1 Programmable extended (debug) port I/O.
-Memory Decoding: Firmware Hub decode, LPC memory decode
-Compatible with LPC specification v1.1 - X-bus Bus Interface (XBI) : Flash Interface
-SPI flash is supported, size up to 4MB.
-SPI frequency supports 33/45/66MHz.
-New SPI command (dual read) to enhance the performance.
-The 64KB code memory can be mapped into system memory by one 16KB and one 48KB programmable pages independently.
-Support SPI flash in-system-programming via IKB pins.
-Enhanced pre-fetch mechanism. - 8051 Microprocessor
-Compatible with industrial 8051 instructions with 3 cycles.
-8051 runs at 8/16/22 MHz, programmable.
-128 bytes internal RAM.
-24 extended interrupt sources.
-Two 16-bit timers.
-Full duplex UART integrated.
-Supports idle and stop mode.
-Enhanced embedded debug interface.
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